Computer hardware engineering: FPGA or ASIC career?

Or application-specific silicon — fixed, expensive, permanent, and shipped in millions of units. The salary gap, the toolchain, the entire shape of the workday, all flow from that single decision.

Pick the wrong lane and the pivot costs years. The honest version of the choice is that it is a choice about the kind of engineer you become. Some want the rhythm of mass production — the satisfaction of a chip that ships in 50 million units and barely changes. Others want the rhythm of iteration — the joy of rewiring a board on a Tuesday afternoon and shipping the fix by Wednesday. Both paths are alive. Both are paying more than they ever have. The question is which version of you the silicon wants you to be.

The fundamental divide: reprogrammable logic versus fixed silicon

The deepest difference between these two paths is almost philosophical. An FPGA — Field-Programmable Gate Array — is a kind of silicon chameleon. It boots up blank, and the engineer pours logic into it from a bitstream, configuring lookup tables, routing wires, and stitching together processors that never existed as physical transistors. The chip can be reprogrammed after deployment, repeatedly, in minutes, by anyone with a JTAG cable and a fresh bitstream.

An ASIC — Application-Specific Integrated Circuit — is the opposite. It is silicon money can't take back. Once the photomasks are made and the wafer spins, the function is etched into the metal. You cannot roll back an ASIC. You can only spin a new one, and the new one costs a fresh round of millions. The chip is fixed at birth, and the engineer who designed it is committed to its silicon for the entire life of the product.

What this means in practice is that computer hardware engineering looks different on each side of the divide. FPGA engineers think in iteration. The chip is a sketchpad. They can change the algorithm, recompile, and reflash in minutes. ASIC engineers think in commitment. The design is closer to a legal document. Every change after sign-off costs weeks and millions. The two mindsets bleed into how engineers approach debugging, how they interact with product managers, and how they plan a multi-year roadmap.

I watched this play out at a tape-out party in Cambridge, Massachusetts, where a chip team had just cleared eighteen months of sign-off on a video transcoder. The relief was visible. The senior designer poured a glass of wine and said, with the kind of fatigue that only comes from permanent decisions, "Now we live with it."

The two paths are not actually strangers. The most common use of an FPGA inside an ASIC company is hardware-assisted verification — building a prototype of the chip on an FPGA before the real silicon spins, so the software team can run real workloads against the design. Many verification engineers begin on FPGAs and end on ASICs, and the verification role is often the bridge between the two worlds. Career paths between them are real, even if they are not painless. The trick is to start where the on-ramp is short and use the verification work as a free graduate degree in the harder craft.

Time-to-market and the economics of NRE costs

ASICs hemorrhage cash before they ship. The non-recurring engineering costs — photomasks, verification, packaging, IP licensing — balloon into the millions of dollars before a single sellable unit leaves the fab. Add a 6 to 18 month time-to-market, and the business case for an ASIC only makes sense when production volumes justify the upfront pain. Spin a chip for a smartwatch that sells 30 million units a year? The math works. Spin one for a satellite constellation that ships 200 units? The math breaks.

FPGAs flip the equation. No masks. No fab commitment. No 18-month gestation. A design that might take a year to harden into silicon can be tested on an FPGA in a week. For defense primes, aerospace prototypes, and any product where the production run is small or the requirements are still moving, the FPGA is the only rational answer. The chip is a bootstrap of the whole product — proof that the architecture works before any silicon is cut.

But the bootstrap doesn't scale. Once a product's volume crosses a threshold, the per-unit cost of an FPGA — the device itself, the power, the board real estate — eclipses what an ASIC would have cost after the NRE is amortized. That is the moment the business case turns, and the FPGA is replaced by its own hardened descendant. Engineers who have watched this transition say it feels like watching a child grow up and move out. The prototype you held together with spit and prayers becomes the production unit shipped to a million customers.

The 6 to 18 month time-to-market number deserves a second look. It is not a runway — it is a gorge. Companies that ship hardware for retail have to predict the chip's market window eighteen months before the chip exists. They are, in effect, betting their product on a forecast, and the forecast is the part of the job that wears ASIC engineers out.

The AI accelerator boom has rewritten this math in a fascinating way. A custom inference chip for a hyperscaler is the most extreme version of the ASIC business case — high NRE, multi-year time-to-market, and the kind of power efficiency that makes the cloud bill survivable. The companies building these chips are not the same ones who used to build general-purpose server CPUs. They are the Googles, the Amazons, the Teslas — companies whose workloads justify the upfront spend, and whose engineers are now among the highest-paid silicon designers in the world.

Performance benchmarks: why ASICs maintain a 3x to 5x speed advantage

The trade-off the FPGA pays for its flexibility is performance. The programmable fabric — the lookup tables, the routing switches, the configurable logic blocks — sits between the engineering and the raw speed of the silicon. Take it away, and the ASIC runs free. Maximum clock speeds in ASICs are typically 3 to 5 times higher than FPGAs, and power efficiency follows the same curve: the ASIC does the same work with less juice, because it has no overhead to be configurable.

Where this matters is not just a benchmark spreadsheet. It is the entire shape of a product. A network switch ASIC from Broadcom handles terabits of traffic at lower latency than any FPGA could manage. A custom AI accelerator — a Cerebras wafer-scale engine, a Google TPU, an Amazon Trainium — beats every FPGA-based equivalent on watts per inference. The hyperscalers have figured out that once their workloads reach a certain scale, the only way to keep the power bill flat is to harden the silicon.

The FPGA is the workhorse. The ASIC is the thoroughbred. Knowing which one your product needs is the first decision a chip architect makes